In IC devices, it is necessary to distribute signals from one area of the IC to another area. For example, in dynamic random access memory (DRAM) ICs, many fuse-triggered signals, and other direct current (DC) or near DC signals are distributed in the IC through a region of the IC called the “spine”. IC design improvements that increase the performance or testability of an IC often increase rather than decrease the number of DC or test mode signals that must be routed through the spine. With increased IC complexity, more signals must be distributed and consequently spine layouts are becoming wire-constrained. However, if the spine height can be reduced, more ICs or chips can be formed on a wafer.
Many of the signals that are distributed in an IC do not change. For example, test mode signals change very infrequently. As a result, it is not necessary to have dedicated conductor wire traces for these signals that occupy critical space in the spine of the IC.
Techniques are needed to reduce the number of conductive traces required for distributing signals in an IC, thereby reducing wire congestion in the spine or other distribution region of an IC.